This invention generally relates to electronic systems and in particular it relates to digital-to-analog converters.
Segmented DACs offer a good compromise between attaining the conflicting goals of high speed and high resolution in modern Nyquist rate DAC applications. The segmented architecture involves the use of thermometer decoded upper segments and thermometer/binary decoded lower segments which are typically derived by a divider circuit driven by a segment identical to the upper segments. The thermometer decoding of the upper and some/all of the lower segments avoids the static and dynamic problems associated with fully binary-weighted implementations due to the large major carry transitions. It is, however, impractical to implement the entire DAC in straight thermometer format with 2n unit elements for n input bits, since of high resolution DACs n is large and the unit elements would number several thousand. The segmented architecture is a compromise between the full binary-weighted architecture and the full thermometer architecture.
Unfortunately the limitations of matching of integrated circuit components limit the static and dynamic accuracy and performance of any DAC, including segmented DACs if no further steps are taken to correct this problem. The inherent matching of components such as MOSFETS, resistors, bipolar transistors, etc., is typically observed to be on the 10-bit level; this creates static nonlinearities and tones in the spectral response of DACs created with such components. In the literature and prior art, a large number of solutions involving trimming, tuning, calibration and similar techniques have been proposed and implemented with regard to this problem. In general, one shortcoming of such techniques is that they offer at most a solution to the static aspect of the problem, in that after the trimming, tuning, calibration, etc., is complete, the unit elements of the DACs are matched at dc or low frequency but not necessarily at higher frequencies. It would be advantageous if the matching would be retained at higher frequencies also. Furthermore, the implementation of these techniques is often complex from the circuit, layout and processing viewpoints. For example, trimming requires increased fabrication complexity and costs due to the need of trimming operations on the wafer, whilst calibration schemes usually involve the addition of some form of storage circuitry onto each unit element being calibrated to store the calibration value.
The solution to these problems should possess the additional feature that it should be able to run in background during the circuit""s normal operation, continuously monitoring the unit element values and correcting them as required. This is desirable to compensate for factors which change over time in integrated circuits, such as temperature and aging/drift processes. Not all the schemes mentioned possess this feature. For example, trimming is a once-only operation which cannot be repeated during normal operation. Similarly, various forms of calibration run in the chip""s foreground and interfere with normal operation, so in applications where this is not acceptable, they can only be run once at power-up.
xe2x80x9cA Noise-Shaping Coder Topology for 15+Bit Convertersxe2x80x9d by L. R. Carley, IEEE Journal of Solid-State Circuits, Volume 24, No. 2, pages 267-273, April 1989, describes a thermometer decoded DAC which uses dynamic element matching (DEM) to randomize the selection order of the thermometer decoded elements, hence restoring linearity both at low and high frequencies. The DAC is not, however, segmented and is suitable only for applications requiring a small number of equally-weighted elements, such as the multibit quantizers used in sigma-delta converter loops. The application of DEM to segmented DACs involves several problems related to mismatch between the upper and lower banks of segments.
To date, DEM has not been used in mainstream Nyquist rate DACs for this reason.
Adams (U.S. Pat. No. 5,977,899) describes a scheme applicable to multibit loop quantizer DACs used for example in sigma-delta feedback loops. The scheme uses DEM again, and also a simple segmented architecture with thermometer decoded upper segments and thermometer decoded lower segments, but relies on noise-shaping to remove the mismatch introduced between these two banks of segments. Such a scheme is only applicable in an over-sampling environment, not a Nyquist-rate application. Furthermore, application of DEM to the lower segments is straightforward only if these segments are also thermometer decoded, which is not the case in general.
Much work has been done on attempts to obtain matching of the DAC elements from interdigitation-based layout of integrated circuit components. Relevant prior art is Mahant-Shetti et al. (U.S. Pat. No. 5,892,471), Tesch et al. (U.S. Pat. No. 5,949,362), and Reynolds (U.S. Pat. No. 5,568,145). In general these works exhibit linearity falling short of the very high accuracy required for modern applications (14bits+). xe2x80x9cA 14 b 150 Msample/s Update Rate Q2 Random Walk CMOS DACxe2x80x9d by J. Vandenbussche et al., International Solid-State Circuits Conference 1999, Digest of Technical Papers, IEEE International, pages 146-147 describes a chip which exhibits such linearity statically, but poor dynamic performance. One contributor to this poor dynamic performance is the large area required for such techniques, which increases parasitics. The large area itself is also inherently undesirable for cost reasons.
Fairchild et al. (U.S. Pat. No. 5,153,592), Smith et al. (U.S. Pat. No. 5,451,946), and Brooks (U.S. Pat. No. 5,446,455) describe schemes which involve measuring the output signal of DACs and compensating them internally accordingly. Such schemes may be applied to most DACs including high speed/precision segmented DACs, but are inherently foreground techniques unless two complete DACs are integrated side-by-side. Furthermore, they offer only a static solution.
Several DACs are based on self-calibrating or error-compensating techniques. Relevant prior art is Gersbach (U.S. Pat. No. 5,642,116), Gersbach (U.S. Pat. No. 5,666,118), Boyacigiller et al. (U.S. Pat. No. 4,465,996), Takeshi et al. (U.S. Pat. No. 5,198,814), Gleim (U.S. Pat. No. 5,270,716), and Hanna (U.S. Pat. No. 5,955,980). These techniques, however, involve complex additional circuitry and offer only static solutions, as is characteristic of calibration schemes, although some may be adapted to run in background.
A general representation of the prior art in segmented DACs is shown in FIG. 1, for the particular case of a current mode DAC where the unit elements are current sources. Those skilled in the art will be very familiar with the circuit architecture shown in this representation. The segmentation is done into a number of upper segments or most significant bits (MSBs) MSB 1 (10), MSB 2 (20) . . . MSB 2 (30), and a number of lower segments 50, 60, and 70, which are derived by dividing a current from an LSB driver current source 40. The prior art thermometer decoder 90 shown in FIG. 2 is used to drive the MSBs of FIG. 1; it does this by creating a thermometer code vector from the n upper bits of the digital input of the DAC which are input to the thermometer decoder 90 on input line 80. The output lines 100, 110, and 120 drives the MSBs 10, 20, and 30 of FIG. 1. Each bit position in this vector corresponds directly to one of the MSB current sources. The lower segments are shown as current sources for convenience, but in actual fact the total current is set by the LSB driver 40 and their function is solely to divide it into least significant bit representations. The implementation of the lower segments could be either thermometer and/or binary-weighted; it is typically a combination of both in high resolution applications, with the lowermost of the lower segments being binary weighted. The LSB Driver 40 is actually optional in the sense that the current sources 50, 60, and 70 could be employed as actual current sources with their tails connected at ground with the appropriate circuit modifications. However, using an LSB Driver is convenient because then it can be treated as an additional 2n MSB for matching purposes. In FIG. 1 the matching requirement is satisfied if all the MSBs as well as the LSB driver are somehow trimmed or calibrated to give the same current value. It is assumed that the matching of the lower segment divider is derived from the inherent component matching of the process used; this is satisfied by allocating no more bits to the lower segments than the inherent component matching of the process can handle (usually 9 or 10 bits). Depending on the implementation, the circuit and method used to equalize the current values can be complex, require a considerable amount of additional circuitry, and possibly require foreground/power-up operation. Finally, only static matching is possible from such trimmed or calibrated architectures. Dynamic performance is not matched in any way except from a best-effort basis in the layout.
Generally, and in one form of the invention, the segmented digital-to-analog converter includes: upper segments; a thermometer decoder; a randomizing circuit coupled between the thermometer decoder and the upper segments for randomizing an output of the thermometer decoder; a divider location selector circuit coupled between the randomizing circuit and the upper segments for choosing a selected segment from the upper segments; and lower segments coupled to the selected segment.